Construction of peripheral area of fingers of power RF LDMOS transistor

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Resumo

A review and study of the design options for the peripherals of RF LDMOS transistor fingers has been carried out. The study was carried out by means of 3D modeling in Sentaurus TCAD. As a result, the design variants allowing to provide the level of the drain-source breakdown voltage at the periphery not lower than in the working part of the finger were determined.

Sobre autores

R. Alekseev

JSC “Scientific Research Institute of Electronic”

Email: arp@niiet.ru
Starykh Bol’shevikov Str., 5, Voronezh, 394033 Russian Federation

P. Prolubnikov

JSC “Scientific Research Institute of Electronic”

Starykh Bol’shevikov Str., 5, Voronezh, 394033 Russian Federation

V. Maltsev

JSC “Scientific Research Institute of Electronic”

Starykh Bol’shevikov Str., 5, Voronezh, 394033 Russian Federation

P. Kurshev

JSC “Scientific Research Institute of Electronic”

Starykh Bol’shevikov Str., 5, Voronezh, 394033 Russian Federation

A. Tsotsorin

JSC “Scientific Research Institute of Electronic”

Starykh Bol’shevikov Str., 5, Voronezh, 394033 Russian Federation

I. Semeykin

JSC “Scientific Research Institute of Electronic”

Starykh Bol’shevikov Str., 5, Voronezh, 394033 Russian Federation

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